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rej03b0229-0010 rev.0.10 apr 01, 2008 page 1 of 53 r8c/32a group renesas mcu 1. overview 1.1 features the r8c/32a group of single-chip mcus incorporates the r8c/tiny series cpu core, employing sophisticated instructions for a high level of effici ency. with 1 mbyte of address space, and it is capable of ex ecuting instructions at high speed. in addition, the cpu core boasts a multiplier for high-speed operation processing. power consumption is low, and the supported operating modes allow additional power control. these mcus also use an anti-noise configuration to reduce emissions of electro magnetic noise and are designed to withstand emi. integration of many peripheral functions, including multifun ction timer and serial inte rface, reduces the number of system components. the r8c/32a group has data flash (1 kb 4 blocks ) with the background operation (bgo) function. 1.1.1 applications electronic household appliances, office equipment, audio equipment, cons umer equipment, etc. rej03b0229-0010 rev.0.10 apr 01, 2008 preliminary notice: this is not a final specification. some parametric limits are subject to change.
r8c/32a group 1. overview rej03b0229-0010 rev.0.10 apr 01, 2008 page 2 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. 1.1.2 specifications tables 1.1 and 1.2 outline the specifications for r8c/32a group. table 1.1 specifications for r8c/32a group (1) item function specification cpu central processing unit r8c/tiny series core ? number of fundamental instructions: 89 ? minimum instruction execution time: 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 2.2 to 5.5 v) 500 ns (f(xin) = 2 mhz, vcc = 1.8 to 5.5 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operation mode: single-chip mode (address space: 1 mbyte) memory rom, ram, data flash refer to table 1.3 product list for r8c/32a group . power supply voltage detection voltage detection circuit ? power-on reset ? voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) i/o ports programmable i/o ports ? input-only: 1 pin ? cmos i/o ports: 15, selectable pull-up resistor ? high current drive ports: 15 clock clock generation circuits 4 circuits: xin clock oscillation circuit, xcin clock oscillation circuit (32 khz) high-speed on-chip oscillator (with frequency adjustment function), low-speed on-chip oscillator, ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: dividing selectable 1, 2, 4, 8, and 16 ? low power consumption modes: standard operating mode (high-speed cl ock, low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode real-time clock (timer re) interrupts ? number of interrupt vectors: 69 ? external interrupt: 7 (int 3, key input 4) ? priority levels: 7 levels watchdog timer ? 15 bits 1 (with prescaler) ? reset start selectable ? low-speed on-chip oscillator for watchdog timer selectable dtc (data transfer controller) ? 1 channel ? activation sources: 21 ? transfer modes: 2 (normal mode, repeat mode) timer timer ra 8 bits 1 (with 8-bit prescaler) timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timer rb 8 bits 1 (with 8-bit prescaler) timer mode (period timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one- shot generation mode timer rc 16 bits 1 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 3 pins), pwm2 mode (pwm output pin) timer re 8 bits 1 real-time clock mode (count seconds, minu tes, hours, days of week), output compare mode
r8c/32a group 1. overview rej03b0229-0010 rev.0.10 apr 01, 2008 page 3 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. note: 1. specify the d version if d ve rsion functions are to be used. table 1.2 specifications for r8c/32a group (2) item function specification serial interface uart0 clock synchronous serial i/o/uart uart2 clock synchronous serial i/o/uart, i 2 c mode (i 2 c-bus), multiprocessor communication function synchronous serial communication unit (ssu) 1 (shared with i 2 c-bus) i 2 c bus 1 (shared with ssu) lin module hardware lin: 1 (timer ra, uart0) a/d converter 10-bit resolution 4 channels, includes sample and hold function, with sweep mode comparator a ? 2 circuits (shared with voltage monitor 1 and voltage monitor 2) ? external reference voltage input available comparator b 2 circuits flash memory ? programming and eras ure voltage: vcc = 2.7 to 5.5 v ? programming and erasure enduranc e: 10,000 times (data flash) 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function ? background operation (bgo) function operating frequency/supply voltage f(xin) = 20 mhz (vcc = 3.0 to 5.5 v) f(xin) = 10 mhz (vcc = 2.7 to 5.5 v) f(xin) = 5 mhz (vcc = 2.2 to 5.5 v) f(xin) = 2 mhz (vcc = 1.8 to 5.5 v) current consumption tbd (vcc = 5.0 v, f(xin) = 20 mhz) tbd (vcc = 3.0 v, f(xin) = 10 mhz) tbd (vcc = 3.0 v, wait mo de (f(xcin) = 32 khz)) tbd (vcc = 3.0 v, stop mode) operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d version) (1) package 20-pin lssop package code: plsp0020jb-a (previous code: 20p2f-a)
r8c/32a group 1. overview rej03b0229-0010 rev.0.10 apr 01, 2008 page 4 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. 1.2 product list table 1.3 lists product list for r8c/32a group, and figure 1.1 shows a part number, memory size, and package of r8c/32a group. (d): under development figure 1.1 part number, memory size, and package of r8c/32a group table 1.3 product list for r8c/32a group current of apr. 2008 part no. rom capacity ram capacity package type remarks program rom data flash r5f21321ansp (d) 4 kbytes 1 kbyte 4 512 bytes plsp0020jb-a n version r5f21322ansp (d) 8 kbytes 1 kbyte 4 1 kbyte plsp0020jb-a r5f21324ansp (d) 16 kbytes 1 kbyte 4 1.5 kbytes plsp0020jb-a r5f21321adsp (d) 4 kbytes 1 kbyte 4 512 bytes plsp0020jb-a d version r5f21322adsp (d) 8 kbytes 1 kbyte 4 1 kbyte plsp0020jb-a r5f21324adsp (d) 16 kbytes 1 kbyte 4 1.5 kbytes plsp0020jb-a part no. r 5 f 21 32 4 a n fp package type: fp: plsp0020jb-a (0.65 mm pin-pitch) classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c rom capacity 1: 4 kb 2: 8 kb 4: 16 kb r8c/32a group r8c/tiny series memory type f: flash memory renesas mcu renesas semiconductor
r8c/32a group 1. overview rej03b0229-0010 rev.0.10 apr 01, 2008 page 5 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram r8c/tiny series cpu core system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout memory rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. 8 port p1 4 port p3 3 1 port p4 timers timer ra (8 bits 1) timer rb (8 bits 1) timer rc (16 bits 1) timer re (8 bits 1) uart or clock synchronous serial i/o (8 bits 2) i 2 c bus or ssu (8 bits 1) peripheral functions watchdog timer (15 bits) a/d converter (10 bits 4 channels) lin module comparator b voltage detection circuit comparator a dtc low-speed on-chip oscillator for watchdog timer
r8c/32a group 1. overview rej03b0229-0010 rev.0.10 apr 01, 2008 page 6 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. 1.4 pin assignment figure 1.3 shows pin assignment (top view). table 1.4 outlines the pin name information by pin number. figure 1.3 pin assignment (top view) 1 2 3 4 5 6 7 8 9 10 20 p1_0/an8/lvcmp1/ki0(/trciod) 19 p1_1/an9/lvcmp2/ki1(/trcioa/trctrg) 18 p1_2/an10/lvref/kl2(/trciob) 17 p1_3/an11/lvcout1/kl3/trbo(/trcioc) 16 p1_4(/txd0/trcclk) 15 p1_5(/int1/rxd0/traio) 14 p1_6/lvcout2/ivref1(/clk0) 13 p1_7/ivcmp1/int1(/traio) 12 p4_5/adtrg/int0(/rxd2/scl2) 11 p3_3/ivcmp3/int3/scs(/cts2/rts2/trcclk) p4_2/vref mode reset p4_7/xout(/xcout) vss/avss p4_6/xin(/xcin) vcc/avcc p3_7/sda/sso/trao(/rxd2/scl2/txd2/sda2) p3_5/scl/ssck(/clk2/trciod) p3_4/ivref3/ssi(/rxd2/scl2/txd2/sda2/trcioc) r8c/32a group plsp0020jb-a (20p2f-a) (top view) notes: 1. can be assigned to the pin in parentheses by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions.
r8c/32a group 1. overview rej03b0229-0010 rev.0.10 apr 01, 2008 page 7 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. note: 1. can be assigned to the pin in parentheses by a program. table 1.4 pin name information by pin number pin number control pin port i/o pin functions for peripheral modules interrupt timer serial interface ssu i 2 c bus a/d converter, comparator a, comparator b, voltage detection circuit 1p4_2 vref 2mode 3 reset 4 xout(/xcout) p4_7 5 vss/avss 6 xin(/xcin) p4_6 7 vcc/avcc 8 p3_7 trao (rxd2/scl2/ txd2/sda2) sso sda 9 p3_5 (trciod) (clk2) ssck scl 10 p3_4 (trcioc) (rxd2/scl2/ txd2/sda2) ssi ivref3 11 p3_3 int3 (trcclk) (cts2 /rts2 )scs ivcmp3 12 p4_5 int0 (rxd2/scl2) adtrg 13 p1_7 int1 (traio) ivcmp1 14 p1_6 (clk0) lvcout2/ivref1 15 p1_5 (int1 ) (traio) (rxd0) 16 p1_4 (trcclk) (txd0) 17 p1_3 ki3 trbo (/trcioc) an11/lvcout1 18 p1_2 ki2 (trciob) an10/lvref 19 p1_1 ki1 (trcioa/ trctrg) an9/lvcmp2 20 p1_0 ki0 (trciod) an8/lvcmp1
r8c/32a group 1. overview rej03b0229-0010 rev.0.10 apr 01, 2008 page 8 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. 1.5 pin functions tables 1.5 and 1.6 list pin functions. i: input o: output i/o: input and output notes: 1. refer to the oscillator manufacturer for oscillation characteristics. 2. to use an externally generated clock, input it to xout. table 1.5 pin functions (1) item pin name i/o type description power supply input vcc, vss ? apply 1.8 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss ? power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xin clock input xin i these pins are provid ed for xin clock generation circuit i/o. connect a ceramic resonator or a crystal oscillator between the xin and xout pins (1) . to use an external clock, input it to the xout pin and leave the xin pin open. xin clock output xout i/o (2) xcin clock input xcin i these pins are provided for xcin clock generation circuit i/o. connect a crystal oscillator between the xcin and xcout pins (1) . to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output xcout o int interrupt input int0 , int1 , int3 iint interrupt input pins. int0 is timer rb, and rc input pin. key input interrupt ki0 to ki3 i key input interrupt input pins timer ra traio i/o timer ra i/o pin trao o timer ra output pin timer rb trbo o timer rb output pin timer rc trcclk i external clock input pin trctrg i external trigger input pin trcioa, trciob, trcioc, trciod i/o timer rc i/o pins serial interface clk0, clk2 i/o transfer clock i/o pins rxd0, rxd2 i serial data input pins txd0, txd2 o serial data output pins cts2 i transmission control input pin rts2 o reception control output pin scl2 i/o i 2 c mode clock i/o pin sda2 i/o i 2 c mode data i/o pin i 2 c bus scl i/o clock i/o pin sda i/o data i/o pin ssu ssi i/o data i/o pin scs i/o chip-select signal i/o pin ssck i/o clock i/o pin sso i/o data i/o pin
r8c/32a group 1. overview rej03b0229-0010 rev.0.10 apr 01, 2008 page 9 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. i: input o: output i/o: input and output table 1.6 pin functions (2) item pin name i/o type description reference voltage input vref i reference voltage input pin to a/d converter a/d converter an8 to an11 i analog input pins to a/d converter adtrg i ad external trigger input pin comparator a lvcmp1, lvcmp2 i comparator a analog voltage input pins lvref i comparator a reference voltage input pin lvcout1, lvcout2 o comparator a output pins comparator b ivcmp1, ivcmp3 i comparator b analog voltage input pins ivref1, ivref3 i comparator b reference voltage input pins voltage detection circuit lvcmp2 i detection voltage input pin for voltage detection 2 i/o port p1_0 to p1_7, p3_3 to p3_5, p3_7, p4_5 to p4_7 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. all ports can be used as led drive ports. input port p4_2 i input-only port
r8c/32a group 2. central processing unit (cpu) rej03b0229-0010 rev.0.10 apr 01, 2008 page 10 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high order bits of intb are intbh and the 16 low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a regist er bank. there are two register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1)
r8c/32a group 2. central processing unit (cpu) rej03b0229-0010 rev.0.10 apr 01, 2008 page 11 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, ar ithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is an alogous to a0. a1 can be comb ined with a0 and as a 32- bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates the starti ng address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operation results in an overflow; otherwise to 0.
r8c/32a group 2. central processing unit (cpu) rej03b0229-0010 rev.0.10 apr 01, 2008 page 12 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i flag is set to 0, and are enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt requ est is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interrupt priority le vels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined.
r8c/32a group 3. memory rej03b0229-0010 rev.0.10 apr 01, 2008 page 13 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. 3. memory 3.1 r8c/32a group figure 3.1 is a memory map of r8c/32a group. the r8 c/32a group has a 1-mbyte address space from addresses 00000h to fffffh. the internal rom (program rom) is allocated lower addresses, beginning with address 0ffffh. for example, a 16-kbyte internal rom area is allocated addresses 0c000h to 0ffffh. the fixed interrupt vector table is allocated addresses 0ffdch to 0ffffh. the starting address of each interrupt routine is stored here. the internal rom (data flash) is al located addresses 03000h to 03fffh. the internal ram is allocat ed higher addresses, beginning with address 00400h. for example, a 1.5-kbyte internal ram area is allocated addresses 00400h to 009ffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. special function registers (sfrs) are allocated addres ses 00000h to 002ffh and 02c0 0h to 02fffh. peripheral function control registers are allocated here. all unallocated spaces within the sfrs are reserved and cannot be accessed by users. figure 3.1 memory map of r8c/32a group 0ffffh 0ffdch notes: 1. data flash indicates block a (1 kbyte), block b (1 kbyte), block c (1 kbyte), and block d (1 kbyte). 2. the blank areas are reserved and cannot be accessed by users. fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom (program rom) internal ram sfr (refer to 4. special function registers (sfrs) ) 02fffh 02c00h sfr (refer to 4. special function registers (sfrs) ) zzzzzh internal rom (program rom) 03fffh 03000h internal rom (data flash) (1) 0ffd8h reserved area undefined instruction overflow brk instruction address match single step watchdog timer, oscillation stop detection, voltage monitor (reserved) (reserved) reset part number r5f21321anfp, r5f21321adfp r5f21322anfp, r5f21322adfp r5f21324anfp, r5f21324adfp internal rom internal ram size address 0yyyyh size address 0xxxxh address zzzzzh 4 kbytes 8 kbytes 16 kbytes 0f000h 0e000h 0c000h 512 bytes 1 kbyte 1.5 kbytes 005ffh 007ffh 009ffh ? ? ?
r8c/32a group 4. special function registers (sfrs) rej03b0229-0010 rev.0.10 apr 01, 2008 page 14 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tables 4.1 to 4.12 list the special function registers. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. the cwr bit in the rstfr register is set to 0 after power-on and voltage monitor 0 reset. software reset, watchdog timer rese t, or oscillation stop detection reset does not affect this bit. 3. the csproini bit in the ofs register is set to 0. 4. the lvdas bit in the ofs register is set to 1. 5. the lvdas bit in the ofs register is set to 0. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 00101000b 0007h system clock control register 1 cm1 00100000b 0008h module standby control register mstcr 00h 0009h system clock control register 3 cm3 00h 000ah protect register prcr 00h 000bh reset source determination register rstfr 0xxx00xxb (2) 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdtc 00111111b 0010h 0011h 0012h 0013h 0014h 0015h high-speed on-chip oscillator control register 7 fra7 when shipping 0016h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (3) 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator control register 1 fra1 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h on-chip reference voltage control register ocvrefcr 00h 0027h 0028h clock prescaler reset flag cpsrf 00h 0029h high-speed on-chip oscillator control register 4 fra4 when shipping 002ah high-speed on-chip oscillator control register 5 fra5 when shipping 002bh high-speed on-chip oscillator control register 6 fra6 when shipping 002ch 002dh 002eh 002fh high-speed on-chip oscillator control register 3 fra3 when shipping 0030h voltage monitor circuit / comparator a control register cmpa 00h 0031h voltage monitor circuit edge select register vcac 00h 0032h 0033h voltage detect register 1 vca1 00001000b 0034h voltage detect register 2 vca2 00h (4) 00100000b (5) 0035h 0036h voltage detection 1 level select register vd1ls 00000111b 0037h 0038h voltage monitor 0 circuit control register vw0c 1100x010b (4) 1100x011b (5) 0039h voltage monitor 1 circuit control register vw1c 10001010b
r8c/32a group 4. special function registers (sfrs) rej03b0229-0010 rev.0.10 apr 01, 2008 page 15 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.2 sfr information (2) (1) x: undefined notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. selectable by the iicsel bit in the ssuiicsr register. address register symbol after reset 003ah voltage monitor 2 circuit control register vw2c 10000010b 003bh 003ch 003dh 003eh 003fh 0040h 0041h flash memory ready interrupt control register fmrdyic xxxxx000b 0042h 0043h 0044h 0045h 0046h 0047h timer rc interrupt control register trcic xxxxx000b 0048h 0049h 004ah timer re interrupt control register treic xxxxx000b 004bh uart2 transmit interrupt control register s2tic xxxxx000b 004ch uart2 receive interrupt control register s2ric xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh ssu interrupt control register / iic bus interrupt control register (2) ssuic / iicic xxxxx000b 0050h 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h 0054h 0055h 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh 005ch 005dh int0 interrupt control register int0ic xx00x000b 005eh uart2 bus collision detection interrupt control register u2bcnic xxxxx000b 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h voltage monitor 1 / compare a1 interrupt control register vcmp1ic xxxxx000b 0073h voltage monitor 2 / compare a2 interrupt control register vcmp2ic xxxxx000b 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh
r8c/32a group 4. special function registers (sfrs) rej03b0229-0010 rev.0.10 apr 01, 2008 page 16 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.3 sfr information (3) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 0080h dtc activation control register dtctl 00h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h dtc activation enable register 0 dtcen0 00h 0089h dtc activation enable register 1 dtcen1 00h 008ah dtc activation enable register 2 dtcen2 00h 008bh dtc activation enable register 3 dtcen3 00h 008ch 008dh dtc activation enable register 5 dtcen5 00h 008eh dtc activation enable register 6 dtcen6 00h 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit / receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit / receive control register 0 u0c0 00001000b 00a5h uart0 transmit / receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h uart2 transmit / receive mode register u2mr 00h 00a9h uart2 bit rate register u2brg xxh 00aah uart2 transmit buffer register u2tb xxh 00abh xxh 00ach uart2 transmit / receive control register 0 u2c0 00001000b 00adh uart2 transmit / receive control register 1 u2c1 00000010b 00aeh uart2 receive buffer register u2rb xxh 00afh xxh 00b0h uart2 digital filter function select register urxdf 00h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh uart2 special mode register 5 u2smr5 00h 00bch uart2 special mode register 4 u2smr4 00h 00bdh uart2 special mode register 3 u2smr3 000x0x0xb 00beh uart2 special mode register 2 u2smr2 x0000000b 00bfh uart2 special mode register u2smr x0000000b
r8c/32a group 4. special function registers (sfrs) rej03b0229-0010 rev.0.10 apr 01, 2008 page 17 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.4 sfr information (4) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 00c0h a/d register 0 ad0 xxxh 000000xxb 00c1h 00c2h a/d register 1 ad1 xxh 00c3h 000000xxb 00c4h a/d register 2 ad2 xxh 00c5h 000000xxb 00c6h a/d register 3 ad3 xxh 00c7h 000000xxb 00c8h a/d register 4 ad4 xxh 00c9h 000000xxb 00cah a/d register 5 ad5 xxh 00cbh 000000xxb 00cch a/d register 6 ad6 xxh 00cdh 000000xxb 00ceh a/d register 7 ad7 xxh 00cfh 000000xxb 00d0h 00d1h 00d2h 00d3h 00d4h a/d mode register admod 00h 00d5h a/d input select register adinsel 11000000b 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h 00e1h port p1 register p1 xxh 00e2h 00e3h port p1 direction register pd1 00h 00e4h 00e5h port p3 register p3 xxh 00e6h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h 00eah port p4 direction register pd4 00h 00ebh 00ech 00edh 00eeh 00efh 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h 00f6h 00f7h 00f8h 00f9h 00fah 00fbh 00fch 00fdh 00feh 00ffh
r8c/32a group 4. special function registers (sfrs) rej03b0229-0010 rev.0.10 apr 01, 2008 page 18 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.5 sfr information (5) (1) note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h lin control register 2 lincr2 00h 0106h lin control register lincr 00h 0107h lin status register linst 00h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register tresec 00h 0119h timer re minute data register / compare data register tremin 00h 011ah timer re hour data register trehr 00h 011bh timer re day of week data register trewk 00h 011ch timer re control register 1 trecr1 00h 011dh timer re control register 2 trecr2 00h 011eh timer re count source select register trecsr 00001000b 011fh 0120h timer rc mode register trcmr 01001000b 0121h timer rc control register 1 trccr1 00h 0122h timer rc interrupt enable register trcier 01110000b 0123h timer rc status register trcsr 01110000b 0124h timer rc i/o control register 0 trcior0 10001000b 0125h timer rc i/o control register 1 trcior1 10001000b 0126h timer rc counter trc 00h 0127h 00h 0128h timer rc general register a trcgra ffh 0129h ffh 012ah timer rc general register b trcgrb ffh 012bh ffh 012ch timer rc general register c trcgrc ffh 012dh ffh 012eh timer rc general register d trcgrd ffh 012fh ffh 0130h timer rc control register 2 trccr2 00011000b 0131h timer rc digital filter function select register trcdf 00h 0132h timer rc output master enable register trcoer 0 1111111b 0133h timer rc trigger control register trcadcr 00h 0134h 0135h 0136h 0137h 0138h 0139h 013ah 013bh 013ch 013dh 013eh 013fh
r8c/32a group 4. special function registers (sfrs) rej03b0229-0010 rev.0.10 apr 01, 2008 page 19 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.6 sfr information (6) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014ah 014bh 014ch 014dh 014eh 014fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015ah 015bh 015ch 015dh 015eh 015fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh
r8c/32a group 4. special function registers (sfrs) rej03b0229-0010 rev.0.10 apr 01, 2008 page 20 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.7 sfr information (7) (1) x: undefined notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. selectable by the iicsel bit in the ssuiicsr register. address register symbol after reset 0180h timer ra pin select register trasr 00h 0181h timer rc pin select register trbrcsr 00h 0182h timer rc pin select register 0 trcpsr0 00h 0183h timer rc pin select register 1 trcpsr1 00h 0184h 0185h 0186h 0187h 0188h uart0 pin select register u0sr 00h 0189h 018ah uart2 pin select register 0 u2sr0 00h 018bh uart2 pin select register 1 u2sr1 00h 018ch ssu / iic pin select register ssuiicsr 00h 018dh 018eh int interrupt input pin select register intsr 00h 018fh 0190h 0191h 0192h 0193h ss bit counter register ssbr 1111 1000b 0194h ss transmit data register l / iic bus transmit data register (2) sstdr / icdrt ffh 0195h ss transmit data register h sstdrh ffh 0196h ss receive data register l / iic bus receive data register (2) ssrdr / icdrr ffh 0197h ss receive data register h (2) ssrdrh ffh 0198h ss control register h / iic bus control register 1 (2) sscrh / iccr1 00h 0199h ss control register l / iic bus control register 2 (2) sscrl / iccr2 0 1111101b 019ah ss mode register / iic bus mode register (2) ssmr / icmr 00011000b 019bh ss enable register / iic bus interrupt enable register (2) sser / icier 00h 019ch ss status register / iic bus status register (2) sssr / icsr 00h / 0000x000b 019dh ss mode register 2 / slave address register (2) ssmr2 / sar 00h 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h flash memory status register fst 10000x00b 01b3h 01b4h flash memory control register 0 fmr0 00h 01b5h flash memory control register 1 fmr1 00h 01b6h flash memory control register 2 fmr2 00h 01b7h 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh
r8c/32a group 4. special function registers (sfrs) rej03b0229-0010 rev.0.10 apr 01, 2008 page 21 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.8 sfr information (8) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 01c0h address match interrupt register 0 rmad0 xxh 01c1h xxh 01c2h 0000xxxxb 01c3h address match interrupt enable register 0 aier0 00h 01c4h address match interrupt register 1 rmad1 xxh 01c5h xxh 01c6h 0000xxxxb 01c7h address match interrupt enable register 1 aier1 00h 01c8h 01c9h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h 01d1h 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh 01e0h pull-up control register 0 pur0 00h 01e1h pull-up control register 1 pur1 00h 01e2h 01e3h 01e4h 01e5h 01e6h 01e7h 01e8h 01e9h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h port p1 drive capacity control register p1drr 00h 01f1h 01f2h drive capacity control register 0 drr0 00h 01f3h drive capacity control register 1 drr1 00h 01f4h 01f5h input threshold control register 0 vlt0 00h 01f6h input threshold control register 1 vlt1 00h 01f7h 01f8h comparator b control register 0 intcmp 00h 01f9h 01fah external input enable register 0 inten 00h 01fbh 01fch int input filter select register 0 intf 00h 01fdh 01feh key input enable register 0 kien 00h 01ffh
r8c/32a group 4. special function registers (sfrs) rej03b0229-0010 rev.0.10 apr 01, 2008 page 22 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.9 sfr information (9) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 2c00h dtc transfer vector area xxh 2c01h dtc transfer vector area xxh 2c02h dtc transfer vector area xxh 2c03h dtc transfer vector area xxh 2c04h dtc transfer vector area xxh 2c05h dtc transfer vector area xxh 2c06h dtc transfer vector area xxh 2c07h dtc transfer vector area xxh 2c08h dtc transfer vector area xxh 2c09h dtc transfer vector area xxh 2c0ah dtc transfer vector area xxh : dtc transfer vector area xxh : dtc transfer vector area xxh 2c3ah dtc transfer vector area xxh 2c3bh dtc transfer vector area xxh 2c3ch dtc transfer vector area xxh 2c3dh dtc transfer vector area xxh 2c3eh dtc transfer vector area xxh 2c3fh dtc transfer vector area xxh 2c40h dtc control data 0 dtcd0 xxh 2c41h xxh 2c42h xxh 2c43h xxh 2c44h xxh 2c45h xxh 2c46h xxh 2c47h xxh 2c48h dtc control data 1 dtcd1 xxh 2c49h xxh 2c4ah xxh 2c4bh xxh 2c4ch xxh 2c4dh xxh 2c4eh xxh 2c4fh xxh 2c50h dtc control data 2 dtcd2 xxh 2c51h xxh 2c52h xxh 2c53h xxh 2c54h xxh 2c55h xxh 2c56h xxh 2c57h xxh 2c58h dtc control data 3 dtcd3 xxh 2c59h xxh 2c5ah xxh 2c5bh xxh 2c5ch xxh 2c5dh xxh 2c5eh xxh 2c5fh xxh 2c60h dtc control data 4 dtcd4 xxh 2c61h xxh 2c62h xxh 2c63h xxh 2c64h xxh 2c65h xxh 2c66h xxh 2c67h xxh 2c68h dtc control data 5 dtcd5 xxh 2c69h xxh 2c6ah xxh 2c6bh xxh 2c6ch xxh 2c6dh xxh 2c6eh xxh 2c6fh xxh
r8c/32a group 4. special function registers (sfrs) rej03b0229-0010 rev.0.10 apr 01, 2008 page 23 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.10 sfr information (10) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 2c70h dtc control data 6 dtcd6 xxh 2c71h xxh 2c72h xxh 2c73h xxh 2c74h xxh 2c75h xxh 2c76h xxh 2c77h xxh 2c78h dtc control data 7 dtcd7 xxh 2c79h xxh 2c7ah xxh 2c7bh xxh 2c7ch xxh 2c7dh xxh 2c7eh xxh 2c7fh xxh 2c80h dtc control data 8 dtcd8 xxh 2c81h xxh 2c82h xxh 2c83h xxh 2c84h xxh 2c85h xxh 2c86h xxh 2c87h xxh 2c88h dtc control data 9 dtcd9 xxh 2c89h xxh 2c8ah xxh 2c8bh xxh 2c8ch xxh 2c8dh xxh 2c8eh xxh 2c8fh xxh 2c90h dtc control data 10 dtcd10 xxh 2c91h xxh 2c92h xxh 2c93h xxh 2c94h xxh 2c95h xxh 2c96h xxh 2c97h xxh 2c98h dtc control data 11 dtcd11 xxh 2c99h xxh 2c9ah xxh 2c9bh xxh 2c9ch xxh 2c9dh xxh 2c9eh xxh 2c9fh xxh 2ca0h dtc control data 12 dtcd12 xxh 2ca1h xxh 2ca2h xxh 2ca3h xxh 2ca4h xxh 2ca5h xxh 2ca6h xxh 2ca7h xxh 2ca8h dtc control data 13 dtcd13 xxh 2ca9h xxh 2caah xxh 2cabh xxh 2cach xxh 2cadh xxh 2caeh xxh 2cafh xxh
r8c/32a group 4. special function registers (sfrs) rej03b0229-0010 rev.0.10 apr 01, 2008 page 24 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.11 sfr information (11) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 2cb0h dtc control data 14 dtcd14 xxh 2cb1h xxh 2cb2h xxh 2cb3h xxh 2cb4h xxh 2cb5h xxh 2cb6h xxh 2cb7h xxh 2cb8h dtc control data 15 dtcd15 xxh 2cb9h xxh 2cbah xxh 2cbbh xxh 2cbch xxh 2cbdh xxh 2cbeh xxh 2cbfh xxh 2cc0h dtc control data 16 dtcd16 xxh 2cc1h xxh 2cc2h xxh 2cc3h xxh 2cc4h xxh 2cc5h xxh 2cc6h xxh 2cc7h xxh 2cc8h dtc control data 17 dtcd17 xxh 2cc9h xxh 2ccah xxh 2ccbh xxh 2ccch xxh 2ccdh xxh 2cceh xxh 2ccfh xxh 2cd0h dtc control data 18 dtcd18 xxh 2cd1h xxh 2cd2h xxh 2cd3h xxh 2cd4h xxh 2cd5h xxh 2cd6h xxh 2cd7h xxh 2cd8h dtc control data 19 dtcd19 xxh 2cd9h xxh 2cdah xxh 2cdbh xxh 2cdch xxh 2cddh xxh 2cdeh xxh 2cdfh xxh 2ce0h dtc control data 20 dtcd20 xxh 2ce1h xxh 2ce2h xxh 2ce3h xxh 2ce4h xxh 2ce5h xxh 2ce6h xxh 2ce7h xxh 2ce8h dtc control data 21 dtcd21 xxh 2ce9h xxh 2ceah xxh 2cebh xxh 2cech xxh 2cedh xxh 2ceeh xxh 2cefh xxh
r8c/32a group 4. special function registers (sfrs) rej03b0229-0010 rev.0.10 apr 01, 2008 page 25 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.12 sfr information (12) (1) x: undefined notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. this register cannot be changed by a program . use a flash programmer to write to it. address register symbol after reset 2cf0h dtc control data 22 dtcd22 xxh 2cf1h xxh 2cf2h xxh 2cf3h xxh 2cf4h xxh 2cf5h xxh 2cf6h xxh 2cf7h xxh 2cf8h dtc control data 23 dtcd23 xxh 2cf9h xxh 2cfah xxh 2cfbh xxh 2cfch xxh 2cfdh xxh 2cfeh xxh 2cffh xxh 2d00h 2d01h ffdbh option function select register 2 ofs2 (note 2) : ffffh option function select register ofs (note 2)
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 26 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. 5. electrical characteristics note: 1. for the register settings for each operation, refer to 7. i/o ports and 9. clock generation circuit of hardware manual (rej09b0458). table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage ? 0.3 to 6.5 v v i input voltage p1_0 to p1_7, p3_3 to p3_5, p3_7, p4_5 to p4_7, mode, reset ? 0.3 to v cc + 0.3 v xin, xout xin-xout oscillation on (oscillation buffer on) (1) ? 0.3 to 1.65 v xin, xout xin-xout oscillation off (oscillation buffer off) (1) ? 0.3 to v cc + 0.3 v xcin xcin-xcout oscillation on (oscillation buffer on) (1) ? 0.3 to 1.65 v xcin xcin-xcout oscillation off (oscillation buffer off) (1) ? 0.3 to v cc + 0.3 v v o output voltage p1_0 to p1_7, p3_3 to p3_5, p3_7, p4_5 to p4_7 ? 0.3 to v cc + 0.3 v xout xin-xout oscillation on (oscillation buffer on) (1) ? 0.3 to 1.65 v xout xin-xout oscillation off (oscillation buffer off) (1) ? 0.3 to v cc + 0.3 v xcout xcin-xcout oscillation on (oscillation buffer on) (1) ? 0.3 to 1.65 v xcout xcin-xcout oscillation off (oscillation buffer off) (1) ? 0.3 to v cc + 0.3 v p d power dissipation t opr = 25 ctbdmw t opr operating ambient temperature ? 20 to 85 (n version) / ? 40 to 85 (d version) c t stg storage temperature ? 65 to 150 c
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 27 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. notes: 1. v cc = 1.8 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. the average output current indicates the av erage value of current measured during 100 ms. table 5.2 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 1.8 ? 5.5 v v ss /av ss supply voltage ? 0 ? v v ih input ?h? voltage input level switching function (i/o port) cmos input input level selection : 0.35 v cc 4.0 v v cc 5.5 v 0.45 v cc ? v cc v 2.7 v v cc < 4.0 v 0.55 v cc ? v cc v 1.8 v v cc < 2.7 v 0.65 v cc ? v cc v input level selection : 0.5 v cc 4.0 v v cc 5.5 v 0.6 v cc ? v cc v 2.7 v v cc < 4.0 v 0.7 v cc ? v cc v 1.8 v v cc < 2.7 v 0.8 v cc ? v cc v input level selection : 0.7 v cc 4.0 v v cc 5.5 v 0.85 v cc ? v cc v 2.7 v v cc < 4.0 v 0.85 v cc ? v cc v 1.8 v v cc < 2.7 v 0.85 v cc ? v cc v vil input ?l? voltage input level switching function (i/o port) cmos input input level selection : 0.35 v cc 4.0 v v cc 5.5 v 0 ? 0.2 v cc v 2.7 v v cc < 4.0 v 0 ? 0.2 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection : 0.5 v cc 4.0 v v cc 5.5 v 0 ? 0.4 v cc v 2.7 v v cc < 4.0 v 0 ? 0.3 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection : 0.7 v cc 4.0 v v cc 5.5 v 0 ? 0.55 v cc v 2.7 v v cc < 4.0 v 0 ? 0.45 v cc v 1.8 v v cc < 2.7 v 0 ? 0.35 v cc v i oh(sum) peak sum output sum of all pins i oh(peak) ?? tbd ma i oh(sum) average sum sum of all pins i oh(avg) ?? tbd ma i oh(peak) peak output ?h? current drive capacity low ??? 10 ma drive capacity high ??? 40 ma i oh(avg) average output ?h? current drive capacity low ??? 5ma drive capacity high ??? 20 ma i ol(sum) peak sum output sum of all pins i ol(peak) ?? tbd ma i ol(sum) average sum sum of all pins i ol(avg) ?? tbd ma i ol(peak) peak output ?l? current drive capacity low ?? 10 ma drive capacity high ?? 40 ma i ol(avg) average output ?l? current drive capacity low ?? 5ma drive capacity high ?? 20 ma f (xin) xin clock input oscillation frequency 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz 1.8 v v cc < 2.2 v 0 ? 2mhz f (xcin) xcin clock input oscillation frequency 1.8 v v cc 5.5 v ? 32.768 50 khz ? foco40m operating when used as the count source for timer rc foco40m = 40mhz 2.7 ? 5.5 v when used as the count source for foco-f foco40m = 40mhz 1.8 ? 5.5 v foco-f foco-f frequency 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz ? foco-s operating voltage foco-s = 125khz 1.8 ? 5.5 v ? system clock frequency 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz 1.8 v v cc < 2.2 v 0 ? 2mhz f (bclk) cpu clock frequency 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz 1.8 v v cc < 2.2 v 0 ? 2mhz
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 28 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. figure 5.1 ports p1, p3, p4 timing measurement circuit p1 p3 p4 30pf
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 29 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. notes: 1. v cc /av cc = v ref = 2.2 to 5.5 v, v ss = 0v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. set ad frequency as follows: when av cc = 4.0 to 5.5 v, 2 mhz ad 20 mhz when av cc = 3.2 to 4.0 v, 2 mhz ad 16 mhz when av cc = 3.0 to 3.2 v, 2 mhz ad 10 mhz when av cc = 2.2 to 3.0 v, 2 mhz ad 5 mhz 3. when the analog input voltage is over the reference voltage, the a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. table 5.3 a/d converter characteristics (1) symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ?? 10 bit inl integral non-linearity error 10-bit mode v ref = av cc = 5.0v an8 to an11 input ?? 3 lsb v ref = av cc = 3.3v an8 to an11 input ?? 5 lsb v ref = av cc = 3.0v an8 to an11 input ?? 5 lsb v ref = av cc = 2.2v an8 to an11 input ?? 5 lsb 8-bit mode v ref = av cc = 5.0v an8 to an11 input ?? 2 lsb v ref = av cc = 3.3v an8 to an11 input ?? 2 lsb v ref = av cc = 3.0v an8 to an11 input ?? 2 lsb v ref = av cc = 2.2v an8 to an11 input ?? 2 lsb ? absolute accuracy 10-bit mode v ref = av cc = 5.0v an8 to an11 input ?? 3 lsb v ref = av cc = 3.3v an8 to an11 input ?? 5 lsb v ref = av cc = 3.0v an8 to an11 input ?? 5 lsb v ref = av cc = 2.2v an8 to an11 input ?? 5 lsb 8-bit mode v ref = av cc = 5.0v an8 to an11 input ?? 2 lsb v ref = av cc = 3.3v an8 to an11 input ?? 2 lsb v ref = av cc = 3.0v an8 to an11 input ?? 2 lsb v ref = av cc = 2.2v an8 to an11 input ?? 2 lsb ? tolerance level impedance ? 3 ? k ? dnl differential non-linearity error ?? 1 lsb ? offset error ?? 3 lsb ? gain error ?? 3 lsb r ladder ladder resistance v ref = av cc 10 ? 40 k ? t conv conversion time 10-bit mode v ref = av cc = 5.0v, ad = 20 mhz 2.0 ?? s 8-bit mode v ref = av cc = 5.0v, ad = 20 mhz 2.0 ?? s t samp sampling time 0.60 ?? s v ref reference voltage 2.2 ? av cc v v ia analog input voltage (3) 0 ? v ref v ocvref on-chip reference voltage 1.24 1.34 1.44 v
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 30 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. note: 1. v cc = 2.7 to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. when the digital filter is not selected. note: 1. v cc = 2.7 to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. when the digital filter is not selected. table 5.4 comparator a electrical characteristics symbol parameter condition standard unit min. typ. max. lvref external reference voltage input range 1.4 ? v cc v lvcmp1, lvcmp2 external comparison voltage input range ? 0.3 ? v cc + 0.3 v ? offset ? tbd tbd mv ? comparator output delay time (2) ? tbd tbd s ? comparator operating current v cc = 5.0 v ? tbd tbd a table 5.5 comparator b electrical characteristics symbol parameter condition standard unit min. typ. max. vref ivref1, ivref3 input reference voltage 0 ? v cc ? 1.4 v v i ivcmp1, ivcmp3 input voltage ? 0.3 ? v cc + 0.3 v ? offset ? tbd tbd mv t d comparator output delay time (2) v i = vref 10 mv ? tbd tbd s i cmp comparator operating current v cc = 5.0 v ? tbd tbd a
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 31 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. notes: 1. v cc = 2.7 to 5.5 v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. 8. the erase sequence does not proceed unles s the interval of 20 ms or more is allowed from when an erase operation starts/restarts until the following suspend is requested. table 5.6 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 1,000 (3) ?? times ? byte program time ? 80 tbd s ? block erase time ? 0.3 tbd s t d(sr-sus) time delay from suspend request until suspend ?? 5+cpu clock 3 cycles ms ? interval from erase start/restart until following suspend request (8) 0 ?? s ? time from suspend until erase restart ?? 30+cpu clock 1 cycle s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ?? year
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 32 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. notes: 1. v cc = 2.7 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. standard of block a to block d when program and erase enduranc e exceeds 1,000 times. byte program time to 1,000 times is the same as that in program rom. 5. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 8. ? 40 c for d version. 9. the data hold time includes time that the po wer supply is off or the clock is not supplied. 10. the erase sequence does not proceed unles s the interval of 3 ms or more is allowed from when an erase operation starts/restarts until the following suspend is requested. figure 5.2 time delay until suspend table 5.7 flash memory (data flash block a to block d) electrical characteristics (4) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ?? times ? byte program time (program/erase endurance 1,000 times) ? 160 tbd s ? byte program time (program/erase endurance > 1,000 times) ? 300 ? s ? block erase time (program/erase endurance 1,000 times) ? 0.2 1 s ? block erase time (program/erase endurance > 1,000 times) ? 0.3 1 s t d(sr-sus) time delay from suspend request until suspend ?? 5+cpu clock 3 cycles ms ? interval from erase start/restart until following suspend request (10) 0 ?? s ? time from suspend until erase restart ?? 30+cpu clock 1 cycle s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature ? 20 (8) ? 85 c ? data hold time (9) ambient temperature = 55 c20 ?? year fst6 bit suspend request (fmr21 bit) fixed time t d(sr-sus) clock-dependent time access restart fst6: bit in fst register fmr21: bit in fmr2 register
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 33 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. notes: 1. the measurement condition is v cc = 1.8 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. select the voltage detection level with bits vdsel0 and vdsel1 in the ofs register. 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca25 bit in the vca2 register to 0. notes: 1. the measurement condition is v cc = 1.8 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. select the voltage detection level with bits vd1s0 to vd1s3 in the vd1ls register. 3. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 4. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. table 5.8 voltage detection 0 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level vdet0_0 (2) at the falling of v cc 1.80 1.90 2.00 v voltage detection level vdet0_1 (2) at the falling of v cc 2.20 2.35 2.50 v voltage detection level vdet0_2 (2) at the falling of v cc 2.70 2.85 3.00 v voltage detection level vdet0_3 (2) at the falling of v cc 3.65 3.80 3.95 v ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? tbd ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? tbd s vccmin mcu operating voltage minimum value 2.2 ?? v table 5.9 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level vdet1_0 (2) at the falling of v cc 2.05 2.20 2.35 v voltage detection level vdet1_1 (2) at the falling of v cc 2.20 2.35 2.50 v voltage detection level vdet1_2 (2) at the falling of v cc 2.35 2.50 2.65 v voltage detection level vdet1_3 (2) at the falling of v cc 2.50 2.65 2.80 v voltage detection level vdet1_4 (2) at the falling of v cc 2.65 2.80 2.95 v voltage detection level vdet1_5 (2) at the falling of v cc 2.80 2.95 3.10 v voltage detection level vdet1_6 (2) at the falling of v cc 2.90 3.10 3.30 v voltage detection level vdet1_7 (2) at the falling of v cc 3.05 3.25 3.45 v voltage detection level vdet1_8 (2) at the falling of v cc 3.20 3.40 3.60 v voltage detection level vdet1_9 (2) at the falling of v cc 3.35 3.55 3.75 v voltage detection level vdet1_a (2) at the falling of v cc 3.50 3.70 3.90 v voltage detection level vdet1_b (2) at the falling of v cc 3.65 3.85 4.05 v voltage detection level vdet1_c (2) at the falling of v cc 3.80 4.00 4.20 v voltage detection level vdet1_d (2) at the falling of v cc 3.95 4.15 4.35 v voltage detection level vdet1_e (2) at the falling of v cc 4.10 4.30 4.50 v voltage detection level vdet1_f (2) at the falling of v cc 4.25 4.45 4.65 v ? voltage monitor 1 interrupt request generation time (3) ? 40 ? s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? tbd ? a t d(e-a) waiting time until voltage detection circuit operation starts (4) ?? tbd s
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 34 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. notes: 1. the measurement condition is v cc = 1.8 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. the voltage detection level varies with detection targets. select the level with the vca24 bit in the vca2 register. 3. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 4. necessary time until the voltage detection circuit operates after setting to 1 again af ter setting the vca27 bit in the vca2 register to 0. notes: 1. the measurement condition is t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. this condition (external power v cc rise gradient) does not apply if v cc 1.0 v. 3. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvd0on bit in the ofs register to 0, the vw0c0 and vw0c6 bits in the vw0c register to 1 respectively, and the vca25 bit in the vca2 register to 1. 4. t w(por1) indicates the duration the external power v cc must be held below the effective voltage (v por1 ) to enable a power on reset. when turning on the power for the first time, maintain t w(por1) for 1 ms or more. figure 5.3 power-on reset circuit electrical characteristics table 5.10 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level vdet2_0 (2) at the falling of v cc 3.80 4.00 4.20 v voltage detection level vdet2_ext (2) at the falling of lvcmp2 1.24 1.34 1.44 v ? voltage monitor 2 interrupt request generation time (3) ? 40 ? s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? tbd ? a t d(e-a) waiting time until voltage detection circuit operation starts (4) ?? tbd s table 5.11 power-on reset circuit, voltage monitor 0 reset electrical characteristics (3) symbol parameter condition standard unit min. typ. max. v por1 power-on reset valid voltage (4) ?? 1.0 v v por2 power-on reset or voltage monitor 0 reset valid voltage 0 ? v det0 v t rth external power v cc rise gradient (2) 20 ?? mv/msec notes: 1. when using the voltage monitor 0 digital filter, ensure that the voltage is within the mcu operation voltage range (1.8 v or above) during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit of hardware manual (rej09b0458) for details. 3. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit of hardware manual (rej09b0458) for details. v det0 (3) v por1 internal reset signal (?l? valid) t w(por1) sampling time (1, 2) v det0 (3) 1 f oco-s 32 1 f oco-s 32 v por2 1.8v external power v cc t rth t rth
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 35 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. notes: 1. v cc = 1.8 to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. this indicates the precision error for the frequency set to foco40m. 3. these values are not guaranteed. 4. this enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in uart mode. note: 1. v cc = 1.8 to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power s upply generation circuit stabilizes during power-on. 3. time until system clock supply starts after the interrupt is acknowledged to exit stop mode. table 5.12 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco40m high-speed on-chip o scillator frequency after reset v cc = 5.0 v, t opr = 25 c tbd (3) 40 tbd (3) mhz high-speed on-chip oscillator frequency when the fra4 register correction value is written into the fra1 register and the fra5 register correction value into the fra3 register (4) tbd (3) 36.864 tbd (3) mhz high-speed on-chip oscillator frequency when the fra6 register correction value is written into the fra1 register and the fra7 register correction value into the fra3 register tbd (3) 32 tbd (3) mhz high-speed on-chip oscillator frequency temperature ? supply voltage dependence (2) v cc = 2.7 v to 5.5 v ? 20 c t opr 85 c tbd ? tbd % v cc = 2.7 v to 5.5 v ? 40 c t opr 85 c tbd ? tbd % v cc = 2.2 v to 5.5 v ? 20 c t opr 85 c tbd ? tbd % v cc = 2.2 v to 5.5 v ? 40 c t opr 85 c tbd ? tbd % v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c tbd ? tbd % v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c tbd ? tbd % ? oscillation st ability time v cc = 5.0 v, t opr = 25 c ? tbd tbd s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? tbd ? a table 5.13 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 60 125 250 khz ? oscillation st ability time v cc = 5.0 v, t opr = 25 c ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 1 ? a table 5.14 power supply circuit timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) ?? tbd s t d(r-s) stop exit time (3) ?? tbd s
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 36 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. notes: 1. v cc = 1.8 to 5.5 v, v ss = 0 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) table 5.15 timing requirements of clock synchronous serial i/o with chip select (1) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ?? t cyc (2) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ?? 1 t cyc (2) slave ?? 1 s t fall ssck clock falling time master ?? 1 t cyc (2) slave ?? 1 s t su sso, ssi data input setup time 100 ?? ns t h sso, ssi data input hold time 1 ?? t cyc (2) t lead scs setup time slave 1t cyc + 50 ?? ns t lag scs hold time slave 1t cyc + 50 ?? ns t od sso, ssi data output delay time ?? 1 t cyc (2) t sa ssi slave access time 2.7 v v cc 5.5 v ?? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ?? 1.5t cyc + 200 ns t or ssi slave out open time 2.7 v v cc 5.5 v ?? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ?? 1.5t cyc + 200 ns
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 37 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. figure 5.4 i/o timing of clock synchronous serial i/o with chip select (master) v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 38 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. figure 5.5 i/o timing of clock synchronous serial i/o with chip select (slave) v ih or v oh v ih or v oh scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 39 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. figure 5.6 i/o timing of clock synchronous serial i/o with chip select (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v ih or v oh
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 40 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. notes: 1. v cc = 1.8 to 5.5 v, v ss = 0 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) figure 5.7 i/o timing of i 2 c bus interface table 5.16 timing requirements of i 2 c bus interface (1) symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ?? ns t sclh scl input ?h? width 3t cyc + 300 (2) ?? ns t scll scl input ?l? width 5t cyc + 500 (2) ?? ns t sf scl, sda input fall time ?? 300 ns t sp scl, sda input spike pulse rejection time ?? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ?? ns t stah start condition input hold time 3t cyc (2) ?? ns t stas retransmit start condition input setup time 3t cyc (2) ?? ns t stop stop condition input setup time 3t cyc (2) ?? ns t sdas data input setup time 1t cyc + 20 (2) ?? ns t sdah data input hold time 0 ?? ns sda t stah t scll t buf v ih v il t sclh scl t sr t sf t sdah t scl t stas t sp t stop t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. retransmit start condition
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 41 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. note: 1. v cc = 4.2 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), f(xin) = 20 mh z, unless otherwise specified. table 5.17 electrical characteristics (1) [v cc = 5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage drive capacity high i oh = ? 20 ma v cc ? 2.0 ? v cc v drive capacity low i oh = ? 5 ma v cc ? 2.0 ? v cc v v ol output ?l? voltage drive capacity high i ol = 20 ma ?? 2.0 v drive capacity low i ol = 5 ma ?? 2.0 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, clk0, clk2, ssi, scl, sda, sso 0.1 0.5 ? v reset 0.1 1.0 ? v i ih input ?h? current vi = 5 v ?? 5.0 a i il input ?l? current vi = 0 v ??? 5.0 a r pullup pull-up resistance vi = 0 v 30 50 167 k ? r fxin feedback resistance xin ? 1.0 ? m ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 42 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 5.18 electrical characteristics (2) [vcc = 5 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6.5 20 ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 5.3 16 ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 3.5 ? ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.1 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 20 mhz low-speed on-chip oscillator on = 125 khz no division ? 6.5 tbd ma xin clock off high-speed on-chip oscillator on foco = 20 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr27 = 1, vca20 = 1 ? 50 400 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr27 = 1, vca20 = 1 ? 60 400 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1, vca20 = 1 ? 30 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 15 tbd a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 4tbd a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (peripheral clock off) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.5 ? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 2.0 tbd a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 5.0 ? a
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 43 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v at topr = 25 c) [v cc = 5 v] figure 5.8 xin input and xcin input timing diagram when v cc = 5 v figure 5.9 traio input timing diagram when v cc = 5 v table 5.19 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input ?h? width 24 ? ns t wl(xin) xin input ?l? width 24 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.20 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 5 v traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio)
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 44 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. i = 0, 2 figure 5.10 serial interface timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.11 input timing for external interrupt int i and key input interrupt kii when vcc = 5 v table 5.21 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.22 external interrupt inti (i = 0, 1, 3) input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) int0 input ?h? width, kii input ?h? width 250 (1) ? ns t w(inl) int0 input ?l? width, kii input ?l? width 250 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0, 2 v cc = 5 v inti input (i = 0, 1, 3) t w(inl) t w(inh) v cc = 5 v kii input (i = 0 to 3)
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 45 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. note: 1. v cc =2.7 to 3.3 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), f(xin) = 10 mh z, unless otherwise specified. table 5.23 electrical characteristics (3) [v cc = 3 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage drive capacity high i oh = ? 5 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v v ol output ?l? voltage drive capacity high i ol = 5 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, clk0, clk2, ssi, scl, sda, sso 0.1 0.3 ? v reset 0.1 0.4 ? v i ih input ?h? current vi = 3 v ?? 4.0 a i il input ?l? current vi = 0 v ??? 4.0 a r pullup pull-up resistance vi = 0 v 66 160 500 k ? r fxin feedback resistance xin ? 3.0 ? m ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 46 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 5.24 electrical characteristics (4) [vcc = 3 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 3.5 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 5.5 tbd ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr27 = 1, vca20 = 1 ? 50 400 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr27 = 1, vca20 = 1 ? 60 400 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1, vca20 = 1 ? 30 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 15 tbd a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 4tbd a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (peripheral clock off) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.5 ? a stop mode xin clock off , t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 2.0 tbd a xin clock off , t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 5.0 ? a
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 47 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v at topr = 25 c) [v cc = 3 v] figure 5.12 xin input and xcin input timing diagram when v cc = 3 v figure 5.13 traio input timing diagram when v cc = 3 v table 5.25 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 100 ? ns t wh(xin) xin input ?h? width 40 ? ns t wl(xin) xin input ?l? width 40 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.26 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 3 v traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio)
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 48 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. i = 0, 2 figure 5.14 serial interface timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.15 input timing for external interrupt int i and key input interrupt kii when vcc = 3 v table 5.27 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.28 external interrupt inti (i = 0, 1, 3) input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) int0 input ?h? width, kii input ?h? width 380 (1) ? ns t w(inl) int0 input ?l? width, kii input ?l? width 380 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v i = 0, 2 t w(inl) t w(inh) v cc = 3 v inti input (i = 0, 1, 3) kii input (i = 0 to 3)
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 49 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. note: 1. v cc = 1.8 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), f(xin) = 5 mhz, unless otherwise specified. table 5.29 electrical characteristics (5) [v cc = 2.2 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage drive capacity high i oh = ? 2 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v v ol output ?l? voltage drive capacity high i ol = 2 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, clk0, clk2, ssi, scl, sda, sso 0.05 0.3 ? v reset 0.05 0.15 ? v i ih input ?h? current vi = 1.8 v ?? 4.0 a i il input ?l? current vi = 0 v ??? 4.0 a r pullup pull-up resistance vi = 0 v 100 200 600 k ? r fxin feedback resistance xin ? 5 ? m ? r fxcin feedback resistance xcin ? 35 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 50 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. table 5.30 electrical characteristics (6) [vcc = 2.2 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 1.8 to 2.7 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 2.2 ? ma xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 0.8 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 5 mhz low-speed on-chip oscillator on = 125 khz no division ? 4 ? ma xin clock off high-speed on-chip oscillator on foco = 5 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.7 ? ma low-speed on- chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr27 = 1, vca20 = 1 ? 50 300 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr27 = 1, vca20 = 1 ? 60 350 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1, vca20 = 1 ? 30 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 15 tbd a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 4tbd a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (peripheral clock off) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.5 ? a stop mode xin clock off , t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 2.0 tbd a xin clock off , t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 5.0 ? a
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 51 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. timing requirements (unless otherwise specified: v cc = 2.2 v, v ss = 0 v at topr = 25 c) [v cc = 2.2 v] figure 5.16 xin input and xcin input timing diagram when v cc = 2.2 v figure 5.17 traio input timing diagram when v cc = 2.2 v table 5.31 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 200 ? ns t wh(xin) xin input ?h? width 90 ? ns t wl(xin) xin input ?l? width 90 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.32 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 500 ? ns t wh(traio) traio input ?h? width 200 ? ns t wl(traio) traio input ?l? width 200 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 2.2 v traio input t c(traio) t wl(traio) t wh(traio) v cc = 2.2 v
r8c/32a group 5. electrical characteristics rej03b0229-0010 rev.0.10 apr 01, 2008 page 52 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. i = 0, 2 figure 5.18 serial interface timing diagram when v cc = 2.2 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.19 input timing for external interrupt int i and key input interrupt kii when vcc = 2.2 v table 5.33 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 800 ? ns t w(ckh) clki input ?h? width 400 ? ns t w(ckl) clki input ?l? width 400 ? ns t d(c-q) txdi output delay time ? 200 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 150 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.34 external interrupt inti (i = 0, 1, 3) input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) int0 input ?h? width, kii input ?h? width 1000 (1) ? ns t w(inl) int0 input ?l? width, kii input ?l? width 1000 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 2.2 v i = 0, 2 t w(inl) t w(inh) v cc = 2.2 v inti input (i = 0, 1, 3) kii input (i = 0 to 3)
r8c/32a group package dimensions rej03b0229-0010 rev.0.10 apr 01, 2008 page 53 of 53 under development preliminary specification specifications in this manual are tentative and subject to change. package dimensions diagrams showing the latest package dimensions and mounti ng information are available in the ?packages? section of the renesas technology website. y index mark 1 10 11 20 f * 1 * 3 * 2 c b p e a d e h e include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. detail f a 1 a 2 l 0.32 0.22 0.17 b p previous code jeita package code renesas code plsp0020jb-a 20p2f-a mass[typ.] 0.1g p-lssop20-4.4x6.5-0.65 0.2 0.15 0.13 max nom min dimension in millimeters symbol reference 6.6 6.5 6.4 d 4.5 4.4 4.3 e 1.15 a 2 6.6 6.4 6.2 1.45 a 0.2 0.1 0 0.7 0.5 0.3 l 10 0 c 0.65 e 0.10 y h e a 1 0.53 0.77
c - 1 revision history r8c/32a group datasheet rev. date description page summary 0.01 oct 26, 2007 ?
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in the event of the failure of a renesas product, such as safety design for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, sinc e the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from r enesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renes as semiconductor products, or if you have any other inquiries. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7858/7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2377-3473 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 3518-3399 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, m alaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 2008. renesas technology corp., all rights reserved. printed in japan. colophon .7.2

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